1. Technical Field
The present disclosure relates, in general, to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a transistor capable of realizing a gate electrode in a fine pitch structure.
2. Discussion of Related Art
Market competitiveness in semiconductor technologies depends to some extent on how many logic devices can be mounted on a small area. Accordingly, one of the most important issues in developing and manufacturing semiconductor products is the downsizing of semiconductor chips. Currently, the downsizing of semiconductor devices is being heavily researched.
When a semiconductor device is highly integrated and downsized, it is difficult to realize a desirable small-sized pattern profile because the minimum allowable line width is reduced. For example, a width of a gate electrode is 500 nm in a 16 MB D-RAM and is reduced to 350 nm in a 64 MB D-RAM. Similarly, the width of the gate electrode is reduced to 250 to 300 nm in a 256 MB D-RAM and to 100 nm or less in a 512 MB D-RAM.
Conventional methods of forming a gate electrode include directly etching a polysilicon layer under a photoresist pattern (hereinafter, referred to as ‘PR pattern’) using the PR pattern as a mask. However, these conventional methods are only applicable to a gate size with a width of 200 nm or more or a gate oxide structure having a thickness of 50 Å or more. This is because it is difficult to control a pattern profile during the etching process because the profile deformation phenomenon of the PR pattern (e.g. collapse of the PR pattern) occurs at 160° C. or higher, and also an overetching phenomenon occurs, in which a portion of the gate oxide is etched when the polysilicon layer is etched, because an etching selectivity to the gate oxide is not sufficiently secured.
Therefore, the above-described conventional method is not suitable for the formation of a thin gate oxide and a small pitch structure except in some special cases.
In other conventional methods the gate electrode is formed using a hard mask made of SiN or SiON. Unlike the conventional method directly using the PR pattern as the mask to form the gate electrode, an etching process using the hard mask includes forming the hard mask using a PR pattern as a mask, and then forming the gate electrode using the hard mask.
According to the conventional etching technology. using the hard mask, a thickness of the gate oxide can be reduced to less than 50 Å (e.g. 10 to 20 Å) and a sectional profile can be controlled in a small-sized gate process while designing the semiconductor device because the etching selectivity of the gate oxide to the PR mask is sufficiently high during etching of the polysilicon layer.
FIGS. 1 to 4 show steps of a conventional method of forming a gate electrode of a transistor using a hard mask. As shown in FIG. 1, a gate oxide 20 is formed on a semiconductor substrate 10, and then a polysilicon layer 30 is formed on the gate oxide 20.
An insulating layer 40 made of Si(O)N which is to be used as a hard mask layer is formed on the polysilicon layer 30. A PR pattern 50 is formed on the insulating layer 40 using a photolithography process. The insulating layer 40 has a thickness of h.
As shown in FIG. 2, a hard mask 40a is formed by etching the insulating layer 40 using the PR pattern 50 as a mask.
As shown in FIG. 3, the PR pattern 50 on the hard mask 40a is removed by an ashing and strip process, with only the hard mask 40a remaining on the polysilicon layer 30.
As shown in FIG. 4, a gate electrode 30a is formed by etching the polysilicon layer 30 using the hard mask 40a. The thickness of the hard mask 40a is reduced to h′ after the completion of the etching process. The reason for the reduction in thickness is that the hard mask 40a is partially consumed when the polysilicon layer 30 is etched.
When a general deposition thickness of the polysilicon layer 30 is 1500 to 2000 Å and an initial deposition thickness (h) of the insulating layer 40 is about 800 Å, a remaining thickness (h′) of the insulating layer is about 200 Å. As a result, the gate electrode 30a with a width of  is formed. The width  that can be realized using this conventional process is about 100 nm.
The hard mask 40a remaining on the gate electrode 30a is then removed using an etchant having a desirable etch selectivity to the polysilicon layer, for example, an ARL (anti-reflective layer) etchant (NAE), thereby accomplishing the process.
The gate electrode 30a may be directly used in subsequent processing or after a silicide layer is formed on the gate electrode 30a. Subsequent processing may include, for example, deposition of an interlayer dielectric (ILD) film or a self-aligned contact (SAC) process without removing the hard mask 40a after the gate electrode 30a is formed.
Although the above-mentioned process can secure an etching selectivity to the thin gate oxide film, it cannot obtain a gate electrode in a fine pitch structure with a width of 100 nm or less. This is because the conventional method cannot form a PR pattern used as a masking layer during the formation of a hard mask with a width of 100 nm or less because of limits in the photolithography process.
Accordingly, there is a need for a process that can fabricate a gate electrode with a width of 100 nm or less to accommodate increased integration of semiconductor devices.